1. Field of the Invention
The present invention relates to a method for integrating an electronic component or the like into a substrate.
2. Description of the Background Art
The modeling of components integrated on a semiconductor substrate is becoming ever more important as operating frequencies increase, since reflections at discontinuities, overlapping, and power dissipation increase in this case. Consequently, in general it is essential to account for these effects in modeling, especially in the high-frequency range. The parasitic influence of substrate conductivity and additional capacitances cannot be ignored, particularly in the case of a low-resistance substrate such as a silicon substrate.
Although it is, in principle, applicable to any desired electronic components, the present invention and the problem on which it is based are by preference described in detail below with reference to a chip to be integrated into the substrate.
The integration of electronic components into a semiconductor substrate and the individual encapsulations have a significant effect on the performance, costs, reliability, and lifetime of the component. In general, unwired subsystems include various components, such as high-frequency transceivers, digital processors, MEMS, or the like. Microwave transceivers, for example, are comprised of both integrated circuits and passive components with filters and power devices, which are not integrated on the semiconductor substrate. These components are based on a variety of materials and technologies.
In the past, considerable improvements have been achieved in the manufacturing and characterization of electronic components, and a number of new components have been developed. The development of compound semiconductors, such as, e.g., gallium arsenide, indium phosphide, and the like, and the development of ternary semiconductors, made it possible to develop microwave and millimeter-wave components with excellent noise and performance characteristics. Microprocessing in the radio frequency range and MEMS have proven to be technologies capable of having a significant impact on existing architectures in the radio frequency range, for example in sensors such as radar sensors in particular, and also in the field of communications, by reducing weight, cost, size, and power dissipation. The technologies required to this end are now available.
Many high-power components have been produced in the past which are intended to be integrated in a semiconductor substrate and can be encapsulated with no loss in power. In this regard, a complete component can include multiple individual components, which are encapsulated one inside the next; an encapsulated system of this nature is called an SOP (System On a Package) system. A primary task in SOP systems is the integration of individual components or chips into a carrier substrate, in essence as a first level of encapsulation.
The conventional art encompasses several methods for integrating individual chips of different materials onto or into a substrate. The most common methods are known as bonding and flip-chip technologies.
Bonding is understood to mean the assembly of, for example, chips on a chip carrier, wherein an individual chip is glued onto a chip carrier by an epoxy adhesive, for example, in a chip bonder. Aluminum or gold wires are generally used for electrically connecting the contact areas of the chip (bond pads) to the associated contact traces of the substrate.
In wedge bonding, the bond wire is held horizontally above the bond area and is pinched off with a wedge-shaped tool, while the excess wire is pulled away.
In ball point bonding, a ball is formed at the end of the bond wire, for example with the aid of a hydrogen flame or an electric spark. The wires used have an approximate diameter of 10 to 25 μm. These very thin wires have a high inductance at higher frequencies. Moreover, changes in their wire lengths and their curved shapes cause disadvantageously varying performance as a function of the particular module.
In addition, flip-chip technology is known in the conventional art. In flip-chip technology, such as is shown in FIG. 2, a chip 8 is placed on a substrate 1 in a downward direction. Solder bumps 14 and adhesive joints, for example filled with conductive powder, serve as connecting means here, ensuring a good electrical connection. The thermal path runs directly through the substrate 1.
However, in this prior art approach it has proven disadvantageous that this thermal path is generally inadequate for reliable operation, for example, in the case of high power gallium arsenide MMICs, so that additional heat removal means must be provided. Another disadvantage of this approach is that the coefficients of thermal expansion of the individual materials used are different, which reduces the lifetime of the component.
Furthermore, efforts have been made to develop new methods for reliably integrating chips based on various materials onto or into a silicon substrate. Illustrated in FIG. 3 is a schematic cross-sectional view of an electronic component 8 integrated in a substrate 1. The substrate 1 is etched from a front side and the chip 8 is attached in the etched cavity by a thermally conductive adhesive.
In addition, an organic dielectric layer 16 is spin-coated onto the front side of the substrate 1 in order to make the surface of the entire wafer flat and smooth. As can also be seen in FIG. 3, suitable metallizations 18 for electrically contacting the chip 8 are provided on the organic dielectric layer 16.
However, it has proven to be a disadvantage in this conventional approach that precise control of the depth of the vertically etched cavity in the substrate 1 is difficult to achieve. Most standard semiconductor manufacturing processes require a maximum difference in height between the chip surface and the wafer surface of 2 μm. Despite the use of the spin-coated organic dielectric layer 16, it is possible to produce an electrical connection to the chip 8, but a planar structure is more desirable. Another disadvantage is that different chips with different overall heights require different cavity depths, so complex and costly etching methods must be used.
Moreover, the high thermal resistance of the structure shown in FIG. 3 presents a disadvantage. Although a thermally conductive adhesive or epoxy is normally used in these methods, these materials have a significantly lower thermal conductivity than silicon or metals such as gold or copper. When an air gap 17 occurs between the chip 8 and the substrate 1, as is shown in FIG. 3, the thermal resistance of the overall structure can even take on a still higher value.
Since thermally conductive adhesives and epoxies have high coefficients of thermal expansion, the structure shown in FIG. 3 has a large thermo-mechanical stress, which significantly and disadvantageously reduces the lifetime of the component as a whole.
Another conventional technology is known as “enhanced quasi-monolithic integration technology (QMIT),” which can be considered an organically deposited multi-chip module (MCM-D). This technology uses a common connection embodied as a thin film for the first level of encapsulation or packaging. Since this technology is still in its infancy, many efforts are currently underway to further improve this technology.